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general description the max13101e/max13102e/max13103e/max13108e 16-bit bidirectional cmos logic-level translators pro- vide the level shifting necessary to allow data transfer in multivoltage systems. these devices are inherently bidirectional due to their design and do not require the use of a direction input. externally applied voltages, v cc and v l , set the logic levels on either side of the devices. logic signals present on the v l side of the device appear as a higher voltage logic signal on the v cc side of the device, and vice-versa. the max13101e/max13102e/max13103e feature an enable input (en) that, when low, reduces the v cc and v l supply currents to less than 2?. the max13108e features a multiplexing input (mult) that selects one byte between the two, thus allowing multiplexing of the signals. the max13101e/max13102e/max13103e/ max13108e have ?5kv esd protection on the i/o v cc side for greater protection in applications that route sig- nals externally. three different output configurations are available during shutdown, allowing the i/o on the v cc side or the v l side to be put in a high-impedance state or pulled to ground through an internal 6k ? resistor. the max13101e/max13102e/max13103e/max13108e accept v cc voltages from +1.65v to +5.5v and v l voltages from +1.2v to v cc , making them ideal for data transfer between low-voltage asics/plds and higher voltage systems. the max13101e/max13102e/ max13103e/max13108e are available in 36-bump ucsp and 40-pin tqfn packages, and operate over the extended -40? to +85? temperature range. applications features ? wide supply voltage range v cc range of 1.65v to 5.5v v l range of 1.2v to v cc ? esd protection on i/o v cc lines 15kv human body model ? up to 20mbps throughput ? low 0.03a typical quiescent current ? ucsp and tqfn packages max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators ________________________________________________________________ maxim integrated products 1 pin configurations 19-3802; rev 2; 8/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information/selector guide continued at end of data sheet. ordering information/selector guide part pin-package data rate (m bps) i/o v l state during shutdown i/o v cc state during shutdown multiplexer feature pkg code max13101e ebx* 36 ucsp** 3.06mm x 3.06mm 20 high impedance 6k ? to gnd no b36-1 max13101eetl 40 tqfn 5mm x 5mm x 0.8mm 20 high impedance 6k ? to gnd no t4055-1 note: all devices operate over the -40? to +85? operating temperature range. max13101e max13102e max13103e tqfn top view of bottom leads 56 4 3 i/o v l 14 i/o v l 16 v l v cc i/o v cc 16 i/o v l 13 i/o v l 3 i/o v l 1 v l i/o v l 4 v cc i/o v cc 1 11 12 i/o v l 7 14 15 16 17 i/o v l 8 i/o v l 9 i/o v cc 7 i/o v cc 8 i/o v cc 9 i/o v cc 10 i/o v l 15 i/o v l 2 13 7 i/o v l 10 i/o v cc 11 8 *exposed paddle connected to ground i/o v l 11 i/o v l 12 en i/o v cc 12 gnd 9 10 i/o v l 6 2 i/o v cc 6 i/o v l 5 1 i/o v cc 5 gnd 26 25 27 28 24 23 22 21 29 30 i/o v cc 15 i/o v cc 14 i/o v cc 13 i/o v cc 2 i/o v cc 3 i/o v cc 4 18 19 20 40 39 37 36 35 34 38 33 32 31 gnd *ep cmos logic-level translation portable equipment cell phones pdas digital still cameras smart phones * future product?ontact factory for availability. **ucsp bumps are in a 6 x 6 array. pin configurations continued at end of data sheet. typical operating circuit appears at end of data sheet. ucsp is a trademark of maxim integrated products, inc.
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +1.65v to +5.5v, v l = +1.2v to v cc , en = v l (max13101e/max13102e/max13103e), mult = v l or gnd (max13108e), t a = t min to t max , unless otherwise noted. typical values are at v cc = +1.65v, v l = +1.2v, t a = +25 c.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc ...........................................................................-0.3v to +6v v l ........................................................................................... -0.3v to +6v i/o v cc_ ......................................................-0.3v to (v cc + 0.3v) i/o v l_ ..................................................................... -0.3v to (v l + 0.3v) en, mult .................................................................-0.3v to +6v short-circuit duration i/o v l_ , i/o v cc_ to gnd .......continuous continuous power dissipation (t a = +70 c) 36-bump ucsp (derate 17.0mw/ c above +70 c) ..1361mw 40-pin tqfn (derate 35.7mw/ c above +70 c) .......2857mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range ............................-65? to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units power supplies v l supply range v l 1.2 v cc v v cc supply range v cc 1.65 5.50 v supply current from v cc i qvcc i/o v cc _ = gnd, i/o v l _ = gnd or i/o v cc _ = v cc , i/o v l _ = v l , en = v l , mult = gnd or v l 0.03 10 ? supply current from v l i qvl i/o v cc _ = gnd, i/o v l _ = gnd or i/o v cc _ = v cc , i/o v l _ = v l , en = v l , mult = gnd or v l 0.03 20 ? v cc shutdown supply current i shdn-vcc t a = +25 c, en = gnd, i/o v cc _ = gnd, i/o v l _ = gnd, max13101e/max13102e/max13103e 0.03 1a v l shutdown supply current i shdn-vl t a = +25 c, en = gnd, i/o v cc _ = gnd, i/o v l _ = gnd, max13101e/max13102e/max13103e 0.03 2a t a = +25 c, en = gnd, max13102e/max13103e 0.02 1 i/o v cc _ tri-state output leakage current t a = + 25 c , m u lt = gn d (i/o v c c 1 - i/o v c c 8) or m u lt = v l ( i/o v c c 9 - i/o v c c 16) m ax 13108e 0.02 1 ? t a = +25 c, en = gnd, max13101e/ max13103e 0.02 1 i/o v l _ tri-state output leakage current t a = +25 c, mult = gnd (i/o v l 1 - i/o v l 8) or mult = v l (i/ov l 9 - i/o v l 16) max13108e 0.02 1 ? i/o v l _ pulldown resistance during shutdown en = gnd, max13102e 4 10 k ?
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +1.65v to +5.5v, v l = +1.2v to v cc , en = v l (max13101e/max13102e/max13103e), mult = v l or gnd (max13108e), t a = t min to t max , unless otherwise noted. typical values are at v cc = +1.65v, v l = +1.2v, t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units i/o v cc _ pulldown resistance during shutdown en = gnd, max13101e 4 10 k ? en or mult input leakage current t a = +25? 1 ? logic-level thresholds i/o v l _ input-voltage high threshold v ihl 2/3 x v l v i/o v l _ input-voltage low threshold v ill 1/3 x v l v i/o v cc _ input-voltage high threshold v ihc 2/3 x v cc v i/o v cc _ input-voltage low threshold v ilc 1/3 x v cc v en, mult input-voltage high threshold v ih-shdn v l - 0.4 v en, mult input-voltage low threshold v il-shdn 0.4 v i/o v l _ output-voltage high v ohl i/o v l _ sour ce cur r ent = 20a, i/o v c c _ v ih c v l - 0.4 v i/o v l _ output-voltage low v oll i/o v l _ sink current = 20?, i/o v cc _ v ilc 0.4 v i/o v cc _ output-voltage high v ohc i/o v c c _ s our ce cur r ent = 20?, i/o v l _ v ih l v c c - 0.4 v i/o v cc _ output-voltage low v olc i/o v cc _ sink current = 20?, i/o v l _ v ill 0.4 v rise/fall-time accelerator stage i/o v cc side v cc / 2 transition-detect threshold i/o v l side v l / 2 v accelerator pulse duration v l = 1.2v, v cc = 1.65v 20 ns v l = 1.2v, v cc = 1.65v 60 i/o v l _ output-accelerator sink impedance v l = 5v, v cc = 5v 5 ? v l = 1.2v, v cc = 1.65v 15 i/o v cc _ output-accelerator sink impedance v l = 5v, v cc = 5v 5 ? v l = 1.2v, v cc = 1.65v 30 i/o v l _ output-accelerator source impedance v l = 5v, v cc = 5v 5 ? v l = 1.2v, v cc = 1.65v 20 i/o v cc _ output-accelerator source impedance v l = 5v, v cc = 5v 7 ? esd protection i/o v cc _ human body model ?5 kv
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 4 _______________________________________________________________________________________ timing characteristics (v cc = +1.65v to +5.5v, v l = +1.2v to v cc , en = v l (max13101e/max13102e/max13103e), mult = v l or gnd (max13108e), t a = t min to t max , unless otherwise noted. typical values are at v cc = +1.65v, v l = +1.2v, t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units i/o v l _ rise time t rvl r s = 50 ? , c i/ovl_ = 15pf, t rise 3ns, (figures 2a, 2b) 15 ns i/o v l _ fall time t fvl r s = 50 ? , c i/ovl_ = 15pf, t fall 3ns, (figures 2a, 2b) 15 ns i/o v cc _ rise time t rvcc r s = 50 ? , c i/ovcc_ = 50pf, t rise 3ns, (figures 1a, 1b) 15 ns i/o v cc _ fall time t fvcc r s = 50 ? , c i/ovcc_ = 50pf, t fall 3ns, (figures 1a, 1b) 15 ns propagation delay (driving i/o v l _) t pvl-vcc r s = 50 ? , c i/ovcc_ = 50pf, t rise 3ns, (figures 1a, 1b) 20 ns propagation delay (driving i/o v cc _) t pvcc-vl r s = 50 ? , c i/ovl_ = 15pf, t rise 3ns, (figures 2a, 2b) 20 ns channel-to-channel skew t skew r s = 50 ? , c i/ovcc_ = 50pf, c i/ovl_ = 15pf, t rise 3ns 5ns part-to-part skew t ppskew r s = 50 ? , c i/ovcc_ = 50pf, c i/ovl_ = 15pf, t rise 3ns, ? t a = +20? (notes 3, 4) 10 ns propagation delay from i/o v l _ to i/o v cc _ after en t en-vcc c i/ovcc_ = 50pf (figure 3) 1 s propagation delay from i/o v cc _ to i/o v l _ after en t en-vl c i/ovl_ = 15pf (figure 4) 1 s maximum data rate r source = 50 ? , c i/ovcc_ = 50pf, c i/ovl_ = 15pf, t rise 3ns 20 mbps note 1: all units are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and not production tested. note 2: for normal operation, ensure that v l < (v cc + 0.3v). during power-up, v l > (v cc + 0.3v) does not damage the device. note 3: v cc from device 1 must equal v cc of device 2. v l from device 1 must equal v l of device 2. note 4: guaranteed by design, not production tested.
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators _______________________________________________________________________________________ 5 t est circuits/timing diagrams max13101e max13102e max13103e max13108e source r s 6k ? 6k ? all unused i/o v cc_ and i/o v l_ connected to gnd i/o v l_ en/(mult) v l v cc i/o v cc_ c i/ovcc_ ( ) are for the max13108e t phl t plh 50% 90% 10% i/o v cc_ i/o v l_ 90% 50% 10% 90% 50% 10% t rise/fall 3ns t fvcc t pvl-vcc = t phl or t plh t rvcc source r s i/o v l_ en/(mult) v l v cc i/o v cc_ c i/ovl_ max13101e max13102e max13103e max13108e 6k ? 6k ? all unused i/o v cc_ and i/o v l_ connected to gnd ( ) are for the max13108e t phl t plh i/o v l_ i/o v cc_ 90% 50% 10% 90% 50% 10% 50% 90% 10% t rise/fall 3ns t fvl t rvl t pvcc-vl = t phl or t plh figure 1a. driving i/o v l_ figure 1b. timing for driving i/o v l_ figure 2a. driving i/o v cc_ figure 2b. timing for driving i/o v cc_
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 6 _______________________________________________________________________________________ _________________________________ t est circuits/timing diagrams (continued) source i/o v cc_ 100k ? i/o v l_ c i/ovcc v l en/(mult) i/o v l_ i/o v cc_ t en-vcc v l v l v cc 0 0 v cc 2 max13101e max13102e max13103e max13108e en/(mult) ( ) are for the max13108e 6k ? 6k ? figure 3. propagation delay from i/o v l_ to i/o v cc_ after en i/o v cc_ i/o v l_ c i/ovl 100k ? v cc en/(mult) i/o v l_ i/o v cc_ t en-vl v l v l v cc 0 0 0 v l 2 source max13101e max13102e max13103e max13108e en/(mult) ( ) are for the max13108e 6k ? 6k ? figure 4. propagation delay from i/o v cc_ to i/o v l_ after en
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators _______________________________________________________________________________________ 7 v l supply current vs. v cc supply voltage (driving i/0 v l_ , v l = 1.8v) v cc supply voltage (v) v l supply current ( a) max13101-3/8e toc01 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 20 40 60 80 100 120 driving one i/o vl figure 1a c i/ovcc_ = 15pf v l supply current vs. v l supply voltage (driving i/0 v cc_ , v cc = 5.5v) v l supply voltage (v) v l supply current ( a) . 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 500 1000 1500 2000 2500 driving one i/o v cc figure 2a c i/ovl_ = 15pf max13101-3/8e toc02 v cc supply current vs. v l supply voltage (driving i/0 v cc_ , v cc = 5.5v) v l supply voltage (v) v cc supply current ( a) max13101-3/8 toc04 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1000 2000 3000 4000 5000 6000 7000 8000 driving one i/o v cc figure 2a c i/ovl_ = 15pf v cc supply current vs. v cc supply voltage (driving i/0 v l_ , v l = 1.8v) v cc supply voltage (v) v cc supply current ( a) max13101-3/8 toc03 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1000 2000 3000 4000 5000 6000 7000 8000 driving one i/o v l figure 1a c i/ovcc_ = 15pf v l supply current vs. temperature (driving i/o v cc_ ) temperature ( c) v l supply current ( a) max13101-3/8e toc05 -40 -15 10 35 60 85 0 100 200 300 400 500 600 700 800 driving one i/o v cc figure 2a c i/ovl_ = 15pf v cc supply current vs. temperature (driving i/o v cc_ ) temperature ( c) v cc supply current ( a) max13101-3/8 toc06 -40 -15 10 35 60 85 0 500 1000 1500 2000 2500 3000 driving one i/o v cc figure 2a c i/ovl_ = 15pf t ypical operating characteristics (v cc = 3.3v, v l = 1.8v, data rate = 20mbps, t a = +25?, unless otherwise noted.)
rise/fall time vs. capacitive load on i/o v l_ (driving i/o v cc_ ) capacitive load (pf) rise/fall time (ns) max13101-3/8e toc10 10 20 30 40 50 0 1 2 3 4 5 6 7 t fvl t rvl figures 2a, 2b propagation delay vs. capacitive load on i/o v cc_ (driving i/o v l_ ) capacitive load (pf) propagation delay (ns) max13101-3/8e toc11 10 20 30 40 50 0 2 4 6 8 10 t plh t phl figures 1a, 1b max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 8 _______________________________________________________________________________________ v l supply current vs. capacitive load on i/o v l_ (driving i/o v cc_ ) capacitive load (pf) v l supply current ( a) max13101-3/8e toc07 10 20 30 40 50 0 200 400 600 800 1000 1200 driving one i/o v cc figure 2a v cc supply current vs. capacitive load on i/o v cc_ (driving i/o v l_ ) capacitive load (pf) v cc supply current ( a) max13101-3/8e toc08 10 20 30 40 50 0 1000 2000 3000 4000 5000 driving one i/o v l figure 1a rise/fall time vs. capacitive load on i/o v cc _ (driving i/o v l_ ) capacitive load (pf) rise/fall time (ns) max13101-3/8e toc09 10 20 30 40 50 0 1 2 3 4 t rvcc t fvcc figures 1a, 1b t ypical operating characteristics (continued) (v cc = 3.3v, v l = 1.8v, data rate = 20mbps, t a = +25?, unless otherwise noted.)
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators _______________________________________________________________________________________ 9 pin description?ax13101e/max13102e/max13103e pin tqfn ucsp name function 1, 21, 30 d6 gnd ground 2 c2 i/o v l 5 input/output 5. referenced to v l . 3 a3 i/o v l 6 input/output 6. referenced to v l . 4 b3 i/o v l 7 input/output 7. referenced to v l . 5 c3 i/o v l 8 input/output 8. referenced to v l . 6 a4 i/o v l 9 input/output 9. referenced to v l . 7 b4 i/o v l 10 input/output 10. referenced to v l . 8 c4 i/o v l 11 input/output 11. referenced to v l . 9 a5 i/o v l 12 input/output 12. referenced to v l . 10 c6 en global enable input. pull en low for shutdown. drive en to v cc or v l for normal operation. 11 b5 i/o v l 13 input/output 13. referenced to v l . 12 c5 i/o v l 14 input/output 14. referenced to v l . 13 a6 i/o v l 15 input/output 15. referenced to v l . 14 b6 i/o v l 16 input/output 16. referenced to v l . 15, 36 a1 v l logic supply voltage, +1.2v v l v cc . bypass v l to gnd with a 0.1? capacitor. 16, 35 f1 v cc v cc supply voltage, +1.65v v cc +5.5v. bypass v cc to gnd with a 0.1? capacitor. for full esd protection, connect a 1.0? capacitor from v cc to gnd, located as close to the v cc input as possible. 17 e6 i/o v cc 16 input/output 16. referenced to v cc . 18 f6 i/o v cc 15 input/output 15. referenced to v cc . rail-to-rail driving (driving i/o v l ) 10ns/div max13101e-3/8e toc13 i/0 v l_ 1v/div i/0 v cc_ 2v/div gnd gnd c i/ovcc_ = 50pf t ypical operating characteristics (continued) (v cc = 3.3v, v l = 1.8v, data rate = 20mbps, t a = +25?, unless otherwise noted.) propagation delay vs. capacitive load on i/o v l_ (driving i/o v cc_ ) capacitive load (pf) propagation delay (ns) max13101-3/8e toc12 10 20 30 40 50 0 1 2 3 4 5 t phl t plh figures 2a, 2b
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 10 ______________________________________________________________________________________ pin description?ax13101e/max13102e/max13103e (continued) pin tqfn ucsp name function 19 d5 i/o v cc 14 input/output 14. referenced to v cc . 20 e5 i/o v cc 13 input/output 13. referenced to v cc . 22 f5 i/o v cc 12 input/output 12. referenced to v cc . 23 d4 i/o v cc 11 input/output 11. referenced to v cc . 24 e4 i/o v cc 10 input/output 10. referenced to v cc . 25 f4 i/o v cc 9 input/output 9. referenced to v cc . 26 d3 i/o v cc 8 input/output 8. referenced to v cc . 27 e3 i/o v cc 7 input/output 7. referenced to v cc . 28 f3 i/o v cc 6 input/output 6. referenced to v cc . 29 d2 i/o v cc 5 input/output 5. referenced to v cc . 31 e2 i/o v cc 4 input/output 4. referenced to v cc . 32 f2 i/o v cc 3 input/output 3. referenced to v cc . 33 d1 i/o v cc 2 input/output 2. referenced to v cc . 34 e1 i/o v cc 1 input/output 1. referenced to v cc . 37 b1 i/o v l 1 input/output 1. referenced to v l . 38 c1 i/o v l 2 input/output 2. referenced to v l . 39 a2 i/o v l 3 input/output 3. referenced to v l . 40 b2 i/o v l 4 input/output 4. referenced to v l . ep ep exposed paddle. connect ep to gnd. pin description?ax13108e pin tqfn ucsp name function 1, 21, 30 d6 gnd ground 2 c2 i/o v l 5 input/output 5. referenced to v l . 3 a3 i/o v l 6 input/output 6. referenced to v l . 4 b3 i/o v l 7 input/output 7. referenced to v l . 5 c3 i/o v l 8 input/output 8. referenced to v l . 6 a4 i/o v l 9 input/output 9. referenced to v l . 7 b4 i/o v l 10 input/output 10. referenced to v l . 8 c4 i/o v l 11 input/output 11. referenced to v l . 9 a5 i/o v l 12 input/output 12. referenced to v l .
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators ______________________________________________________________________________________ 11 pin description?ax13108e (continued) pin tqfn ucsp name function 10 c6 mult multiplexing input. drive mult low to enable channels 9 to 16. driving mult low puts channels 1 to 8 into tri-state. drive mult to v cc or v l to enable channels 1 to 8. driving mult to v cc or v l puts channels 9 to 16 into tri-state. 11 b5 i/o v l 13 input/output 13. referenced to v l . 12 c5 i/o v l 14 input/output 14. referenced to v l . 13 a6 i/o v l 15 input/output 15. referenced to v l . 14 b6 i/o v l 16 input/output 16. referenced to v l . 15, 36 a1 v l logic supply voltage, +1.2v v l v cc . bypass v l to gnd with a 0.1? capacitor. 16, 35 f1 v cc v cc supply voltage, +1.65v v cc +5.5v. bypass v cc to gnd with a 0.1? capacitor. for full esd protection, connect a 1.0? capacitor from v cc to gnd, located as close to the v cc input as possible. 17 e6 i/o v cc 16 input/output 16. referenced to v cc . 18 f6 i/o v cc 15 input/output 15. referenced to v cc . 19 d5 i/o v cc 14 input/output 14. referenced to v cc . 20 e5 i/o v cc 13 input/output 13. referenced to v cc . 22 f5 i/o v cc 12 input/output 12. referenced to v cc . 23 d4 i/o v cc 11 input/output 11. referenced to v cc . 24 e4 i/o v cc 10 input/output 10. referenced to v cc . 25 f4 i/o v cc 9 input/output 9. referenced to v cc . 26 d3 i/o v cc 8 input/output 8. referenced to v cc . 27 e3 i/o v cc 7 input/output 7. referenced to v cc . 28 f3 i/o v cc 6 input/output 6. referenced to v cc . 29 d2 i/o v cc 5 input/output 5. referenced to v cc . 31 e2 i/o v cc 4 input/output 4. referenced to v cc . 32 f2 i/o v cc 3 input/output 3. referenced to v cc . 33 d1 i/o v cc 2 input/output 2. referenced to v cc . 34 e1 i/o v cc 1 input/output 1. referenced to v cc . 37 b1 i/o v l 1 input/output 1. referenced to v l . 38 c1 i/o v l 2 input/output 2. referenced to v l . 39 a2 i/o v l 3 input/output 3. referenced to v l . 40 b2 i/o v l 4 input/output 4. referenced to v l . ep ep exposed paddle. connect ep to gnd.
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 12 ______________________________________________________________________________________ en v cc i/o v l 1 i/o v l 2 i/o v l 3 i/o v l 4 i/o v l 5 i/o v l 6 i/o v l 7 i/o v l 8 i/o v l 9 i/o v l 10 i/o v l 11 i/o v l 12 i/o v l 13 i/o v l 14 i/o v l 15 i/o v l 16 i/o v cc 1 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v cc 6 i/o v cc 7 i/o v cc 8 i/o v cc 9 i/o v cc 10 i/o v cc 11 i/o v cc 12 i/o v cc 13 i/o v cc 14 i/o v cc 15 gnd i/o v cc 16 v l max13101e max13102e max13103e functional diagrams mult i/o v l 1 i/o v l 2 i/o v l 3 i/o v l 4 i/o v l 5 i/o v l 6 i/o v l 7 i/o v l 8 i/o v l 9 i/o v l 10 i/o v l 11 i/o v l 12 i/o v l 13 i/o v l 14 i/o v l 15 i/o v l 16 i/o v cc 1 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v cc 6 i/o v cc 7 i/o v cc 8 i/o v cc 9 i/o v cc 10 i/o v cc 11 i/o v cc 12 i/o v cc 13 i/o v cc 14 i/o v cc 15 i/o v cc 16 gnd max13108e v l v cc
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators ______________________________________________________________________________________ 13 detailed description the max13101e/max13102e/max13103e/max13108e logic-level translators provide the level shifting neces- sary to allow data transfer in a multivoltage system. externally applied voltages, v cc and v l , set the logic levels on either side of the device. logic signals pre- sent on the v l side of the device appear as a higher voltage logic signal on the v cc side of the device, and vice-versa. the max13101e/max13102e/max13103e/ max13108e are bidirectional level translators allowing data translation in either direction (v l ? v cc ) on any single data line. the max13101e/max13102e/ max13103e/max13108e accept v l from +1.2v to v cc . all devices have a v cc range from +1.65v to +5.5v, making them ideal for data transfer between low-volt- age asics/plds and higher voltage systems. the max13101e/max13102e/max13103e feature an output enable mode that reduces v cc supply current to less than 1?, and v l supply current to less than 2? when in shutdown. the max13108e features a multi- plexing input that selects one byte between the two, thus allowing multiplexing of the signals. the max13101e/max13102e/max13103e/max13108e have ?5kv esd protection on the i/o v cc side for greater protection in applications that route signals externally. the max13101e/max13102e/max13103e/ max13108e operate at a guaranteed data rate of 20mbps. the maximum data rate depends heavily on the load capacitance (see the typical operating characteristics ) and the output impedance of the external driver. power-supply sequencing for proper operation, ensure that +1.65v v cc +5.5v, +1.2v v l +5.5v, and v l v cc . during power-up sequencing, v l v cc does not damage the device. when v cc is disconnected and v l is powering up, up to 10ma of current can be sourced to each load on the v l side, yet the device does not latch up. to guarantee that no excess leakage current flows and that the device does not interfere with the i/o on the v l side, v cc should be connected to gnd with a max 50 ? resistor when the v cc supply is not present (figure 5). input driver requirements the max13101e/max13102e/max13103e/max13108e architecture is based on a one-shot accelerator output stage (figure 6). accelerator output stages are always in tri-state except when there is a transition on any of the translators on the input side, either i/o v l _ or i/o v cc _. then a short pulse is generated, during which the accelerator output stages become active and charge/discharge the capacitances at the i/os. due to the bidirectional nature, both input stages become active during the one-shot pulse. this can lead to some current feeding into the external source that is driving the translator. however, this behavior helps to speed up the transition on the driven side. for proper full-speed operation, the output current of a device that drives the inputs of the max13101e/ max13102e/max13103e/max13108e should meet the following requirement: i > 10 8 x v x (c + 10pf) where, i is the driver output current, v is the logic-supply voltage (i.e., v l or v cc ) and c is the parasitic capaci- tance of the signal line. enable output mode (en) the max13101e/max13102e/max13103e feature an enable input (en) that, when driven low, places the device into shutdown mode. during shutdown, the max13101e i/o v cc _ ports are pulled down to ground with internal 6k ? resistors and the i/o v l _ ports enter tri-state. max13102e i/o v cc _ lines enter tri-state and the i/ov l _ lines are pulled down to ground with internal 6k ? resistors. all i/o v cc _ and i/o v l _ lines on the max13103e enter tri-state while the device is in shut- down mode. during shutdown, the v cc supply current reduces to less than 1a, and the v l supply current reduces to less than 2?. to guarantee minimum shut- down supply current, all i/o v l _ need to be driven to gnd or v l , or pulled to gnd or v l through 100k ? resistors. all i/o v cc _ need to be driven to gnd or v cc, or pulled to gnd or v cc through 100k ? resistors. drive en to logic-high (v l or v cc ) for normal operation. i/o v cc 16 i/o v l 16 i/o v l 1 i/o v cc 1 v cc v l +1.2v to +5.5v gnd v cc supply v batt disable r dson < 50 ? max13101e max13102e max13103e max13108e figure 5. recommended circuit for powering down v cc
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 14 ______________________________________________________________________________________ multiplexing input (mult) the max13108e features a multiplexing input (mult) that enables 8 of the 16 channels and places the remaining 8 into tri-state. figure 7 depicts a typical mul- tiplexing configuration using the max13108e. drive mult high to enable i/o v cc 1 through i/o v cc 8 and i/o v l 1 through i/o v l 8. driving mult high sets i/o v cc 9 through i/o v cc 16 and i/o v l 9 through i/o v l 16 into tri-state. drive mult low to enable i/o v cc 9 through i/o v cc 16 and i/o v l 9 through i/o v l 16. driving mult low sets i/o v cc 1 through i/o v cc 8 and i/o v l 1 through i/o v l 8 into tri-state. ?5kv esd protection as with all maxim devices, esd-protection structures are incorporated on all pins to protect against electro- static discharges encountered during handling and assembly. the i/o v cc _ lines have extra protection against static discharge. maxim? engineers have devel- oped state-of-the-art structures to protect these pins against esd of ?5kv without damage. the esd struc- tures withstand high esd in all states: normal operation, tri-state output mode, and powered down. after an esd event, maxim? e versions keep working without latchup, whereas competing products can latch and must be powered down to remove the latchup condition. esd protection can be tested in various ways. the i/o v cc _ lines of the max13101e/ max13102e/ max13103e/ max13108e are characterized for protec- tion to ?5kv using the human body model. rise-time accelerator fall-time accelerator i/o v cc_ i/o v l_ v cc v l rise-time accelerator fall-time accelerator max13101e max13102e max13103e max13108e figure 6. simplified diagram (1 i/o line) port a port b i/o v l 9 i/o v l 10 i/o v l 11 i/o v l 12 i/o v l 13 i/o v l 14 i/o v l 15 i/o v l 16 i/o v l 3 i/o v l 4 i/o v l 5 i/o v l 6 i/o v l 7 i/o v l 8 i/o v l 1 i/o v l 2 i/o v cc 1 mult i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v cc 6 i/o v cc 7 i/o v cc 8 i/o v cc 9 i/o v cc 10 i/o v cc 11 i/o v cc 12 i/o v cc 13 i/o v cc 14 i/o v cc 15 i/o v cc 16 max13108e figure 7. max13108e multiplexing configuration
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators ______________________________________________________________________________________ 15 esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 8a shows the human body model and figure 8b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the test device through a 1.5k ? resistor. machine model the machine model for esd tests all pins using a 200pf storage capacitor and zero discharge resis- tance. its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. all pins require this protection during manufacturing, not just inputs and outputs. therefore, after pc board assembly, the machine model is less relevant to i/o ports. applications information power-supply decoupling to reduce ripple and the chance of transmitting incor- rect data, bypass v l and v cc to ground with 0.1? capacitors. to ensure full ?5kv esd protection, bypass v cc to ground with a 1f ceramic capacitor. place all capacitors as close to the power-supply inputs as possible. capacitive loading capacitive loading on the i/o lines impacts the rise time (and fall time) of the max13101e/max13102e/ max13103e/max13108e when driving the signal lines. the actual rise time is a function of the parasitic capaci- tance, the supply voltage, and the drive impedance of the max13101e/max13102e/max13103e/max13108e. for proper operation, the signal must reach the v oh as required before the rise-time accelerators turn off. high- voltage dc source device under test r c 1m ? r d 1500 ? charge-current- limit resistor discharge resistance storage capacitor c s 100pf figure 8a. human body esd test model 100% 90% 36.8% t rl t dl time current waveform peak-to-peak ringing (not drawn to scale) 10% 0 0 amperes i p i r figure 8b. human body model current waveform
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 16 ______________________________________________________________________________________ ordering information/selector guide (continued) part pin-package data rate (m bps) i/o v l state during shutdown i/o v cc state during shutdown multiplexer feature pkg code max13102e ebx* 36 ucsp** 3.06mm x 3.06mm 20 6k ? to gnd high impedance no b36-1 max13102eetl 40 tqfn 5mm x 5mm x 0.8mm 20 6k ? to gnd high impedance no t4055-1 max13103e ebx* 36 ucsp** 3.06mm x 3.06mm 20 high impedance high impedance no b36-1 max13103eetl 40 tqfn 5mm x 5mm x 0.8mm 20 high impedance high impedance no t4055-1 max13108e ebx* 36 ucsp** 3.06mm x 3.06mm 20 high impedance high impedance yes b36-1 max13108eetl 40 tqfn 5mm x 5mm x 0.8mm 20 high impedance high impedance yes t4055-1 pin configurations (continued) ma131018e tqfn top view of bottom leads 56 4 3 i/o v l 14 i/o v l 16 v l v cc i/o v cc 16 i/o v l 13 i/o v l 3 i/o v l 1 v l i/o v l 4 v cc i/o v cc 1 11 12 i/o v l 7 14 15 16 17 i/o v l 8 i/o v l 9 i/o v cc 7 i/o v cc 8 i/o v cc 9 i/o v cc 10 i/o v l 15 i/o v l 2 13 7 i/o v l 10 i/o v cc 11 8 * exposed paddle connected to ground i/o v l 11 i/o v l 12 mult i/o v cc 12 gnd 9 10 i/o v l 6 2 i/o v cc 6 i/o v l 5 1 i/o v cc 5 gnd 26 25 27 28 24 23 22 21 29 30 i/o v cc 15 i/o v cc 14 i/o v cc 13 i/o v cc 2 i/o v cc 3 i/o v cc 4 18 19 20 40 39 37 36 35 34 38 33 32 31 gnd *ep note: all devices operate over the -40? to +85? operating temperature range. * future product?ontact factory for availability. **ucsp bumps are in a 6 x 6 array.
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators ______________________________________________________________________________________ 17 pin configurations (continued) 1 23456 e d f ucsp (bottom view) ucsp (bottom view) i/o v cc 3 i/o v cc 6 i/o v cc 9 i/o v cc 12 i/o v cc 15 i/o v cc 1 i/o v cc 4 i/o v cc 7 i/o v cc 10 i/o v cc 13 i/o v cc 16 i/o v cc 2 i/o v cc 5 i/o v cc 8 i/o v cc 11 i/o v cc 14 gnd i/o v l 2 i/o v l 5 i/o v l 8 i/o v l 11 i/o v l 14 en i/o v l 1 i/o v l 4 i/o v l 7 i/o v l 10 i/o v l 13 i/o v l 16 v l i/o v l 3 i/o v l 6 i/o v l 9 i/o v l 12 i/o v l 15 b a c max13101e/max13102e/max13103e 1234 56 e d f v cc v cc i/o v cc 3 i/o v cc 6 i/o v cc 9 i/o v cc 12 i/o v cc 15 i/o v cc 1 i/o v cc 4 i/o v cc 7 i/o v cc 10 i/o v cc 13 i/o v cc 16 i/o v cc 2 i/o v cc 5 i/o v cc 8 i/o v cc 11 i/o v cc 14 gnd i/o v l 2 i/o v l 5 i/o v l 8 i/o v l 11 i/o v l 14 mult i/o v l 1 i/o v l 4 i/o v l 7 i/o v l 10 i/o v l 13 i/o v l 16 v l i/o v l 3 i/o v l 6 i/o v l 9 i/o v l 12 i/o v l 15 b a c max13108e chip information process: bicmos t ypical operating circuit max13101e max13102e max13103e max13108e +1.8v +3.3v +1.8v system controller +3.3v system data ( ) are for max13108e data gnd v l v cc i/o v cc_ i/o v l_ en/(mult)
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators 18 ______________________________________________________________________________________ 36l,ucsp.eps j 1 1 21-0082 package outline, 6x6 ucsp pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max13101e/max13102e/max13103e/max13108e 16-channel buffered cmos logic-level translators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. 40l thin qfn.eps a 1 2 21-0159 package outline, 40l thin qfn 5x5x0.8mm body / 0.4mm lead pitch notes: 1. all dimensions are in millimeters. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length / package width are considered as special characteristics. (s) ne nd n l1 l0.400 0.300 10 40 10 0.400 0.500 0.500 0.600 min. pkg. max. nom. min. ol ymb s s 0.200 ref. 0.400 typ. 4.900 d e k k1 e 4.900 0.250 0.350 a1 a2 b a 0.150 0.700 0.000 5.100 5.000 5.100 5.000 0.350 0.450 0.450 0.550 0.200 0.250 0.750 -- -- 0.800 0.050 t4055-1 code common dimensions d2 e2 3.20 min. 3.30 nom. 3.20 max. 3.40 nom. 3.30 max. 3.40 exposed pad variatons a 2 2 21-0159 package outline, 40l thin qfn 5x5x0.8mm body / 0.4mm lead pitch 5. refer to jedec mo-220. 6. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 7. nd and ne refer to the number of terminals on each d and e side respectively. identifier may be either a mold or marked feature. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > i nterfac e and i nterc onnec t max13101e, max13102e, max13103e, max13108e 16-c hannel buffered c mos logic-level translators quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-14 of 14 m ax13101e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max13101eetl+t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13101eetl+ thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13101eetl thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis max13101eetl-t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis m ax13102e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max13102eetl+t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13102eetl+ thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis m ax13103e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max13103eetl+t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13103eetl+ thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13103eetl-t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis max13103eetl thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis m ax13108e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is
max13108eetl+ thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13108eetl+t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13108eetl-t thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis max13108eetl thin qfn;40 pin;26 mm dwg: 21-0140l (pdf) use pkgcode/variation: t4055-1 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -3 8 0 2 ; rev 2 ; 2 0 0 6 -0 8 -1 4 t his page las t modified: 2 0 0 6 -0 8 -1 5 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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